Generally, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. As transistors are reduced in size (CMOS scaling), the demands on lithographic tools have increased. Lithographic tools are utilized to form structures on the integrated circuit. For example, lithographic tools can be utilized to define gate conductors, conductive lines, vias, doped regions, and other structures associated with an integrated circuit.
In one type of conventional fabrication process, a photoresist is lithographically patterned by providing electromagnetic radiation such as ultraviolet light through an overlay. A conventional lithographic system is generally utilized to project the pattern to the photoresist material or layer. The photoresist material may be either a positive or a negative photoresist layer.
As the size of features on the integrated circuit reach sizes below 100 and even 50 nanometers, lithographic techniques are unable to precisely and accurately define the feature. For example, it is frequently desirous to reduce the width of the gate (the gate length) associated with a transistor. Future designs of transistors could require a gate conductor having a width of less than 50 nm.
In the case of a positive photoresist material or layer, the light causes photochemical reaction in the photoresist layer. The photoresist layer is removable with a developer solution at the portions of the photoresist that are exposed to light through a mask. The photoresist layer is developed to clear away those portions. An integrated circuit feature, such as a gate, via, or interconnect, is etched or doped into the layer of material, and the remaining photoresist is removed. In the case of a negative photoresist material, the light causes the photoresist layer to be removable with a developer solution at portions of the photoresist layer that are not exposed to light through the mask.
Various types of photoresist materials are manufactured by a number of manufacturers. The photoresist material can include multiple photoresist films (i.e. a multi-level resist (MLR)). According to some conventional processes, the photoresist layer is provided over an anti-reflective coating (ARC), such as silicon nitride (Si3N4) or silicon oxynitride (SiON). The anti-reflective coating is disposed above the material which is to be processed.
Conventional processes have utilized a variety of resolution enhancement technologies for lithographically creating patterns which define lines and spaces. These processes include the use of phase shift masks, resist enhancement lithography assisted by chemical shrink (RELACS), the use of reflow operations and the use of ultrathin photoresist layers.
RELACS techniques by Clariant AZ utilizes a polymer with an R2 coating and R200 developer to shrink the size of contact holes. The RELACS process can use a coat, diffusion bake and rinse step after wafer patterning.
T-shaped gate conductors have been considered for future designs. T-shaped gate conductors can reduce the resistance associated with small gate lengths due to the large gate width at the top transistor and yet achieve densely packed transistors due to the small gate width at the bottom. Heretofore, T-shaped gate conductors have not been formed according to resolution enhancement.
Thus, there is a need for a method of making a novel transistor structure which is less susceptible to gate resistance and yet has an acceptable size. Further still, there is a need for a dual damascene method for manufacturing a gate structure. Even, further still, there is a need for a method of fabricating a gate structure which provides a gate conductor having a width less than a width achievable by conventional lithographic techniques.